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Inter-integrated circuit (I 2 C) interface
RM0008
24.6.6
Status register 1 (I2C_SR1)
Address offset: 0x14
Reset value: 0x0000
15
SMB
ALERT
rc_w0
14
TIME
OUT
rc_w0
13
Res.
12
PEC
ERR
rc_w0
11
OVR
rc_w0
10
AF
rc_w0
9
ARLO
rc_w0
8
BERR
rc_w0
7
TxE
r
6
RxNE
r
5
Res.
4
STOP
F
r
3
ADD10
r
2
BTF
r
1
ADDR
r
0
SB
r
Bit 15 SMBALERT : SMBus alert
In SMBus host mode:
0: no SMBAlert
1: SMBAlert event occurred on pin
In SMBus slave mode:
0: no SMBAlert response address header
1: SMBAlert response address header to SMBAlert LOW received
– Cleared by software writing 0, or by hardware when PE=0.
Bit 14 TIMEOUT : Timeout or Tlow error
0: No timeout error
1: SCL remained LOW for 25 ms (Timeout)
or
Master cumulative clock low extend time more than 10 ms (Tlow:mext)
or
Slave cumulative clock low extend time more than 25 ms (Tlow:sext)
– When set in slave mode: slave resets the communication and lines are released by
hardware
– When set in master mode: Stop condition sent by hardware
– Cleared by software writing 0, or by hardware when PE=0.
Bit 13 Reserved, forced by hardware to 0.
Bit 12 PECERR : PEC Error in reception
0: no PEC error: receiver returns ACK after PEC reception (if ACK=1)
1: PEC error: receiver returns NACK after PEC reception (whatever ACK)
–Cleared by software writing 0, or by hardware when PE=0.
Bit 11 OVR : Overrun/Underrun
0: No overrun/underrun
1: Overrun or underrun
–Set by hardware in slave mode when NOSTRETCH=1 and:
–In reception when a new byte is received (including ACK pulse) and the DR register has
not been read yet. New received byte is lost.
–In transmission when a new byte should be sent and the DR register has not been written
yet. The same byte is sent twice.
–Cleared by software writing 0, or by hardware when PE=0.
Note: If the DR write occurs very close to SCL rising edge, the sent data is unspecified and a
hold timing error occurs
646/995
Doc ID 13902 Rev 9
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